1. Field of the Invention
The invention relates to, and more particularly, to a circuit and a method for generating a high frequency signal by realizing frequency multiplication on low frequency signals, and more particularly to, a circuit and a method for generating a high frequency signal by realizing frequency multiplication on low frequency signals by a delay-locked loop or delay-locked loop.
2. Description of the Prior Art
In this modern society, all sorts of information, data, documents, communications, and audio and video signals are encoded in electrical format to increase the speed and efficiency for transmitting, processing, calculating, and storing. As a result, a variety of electrical circuits that are used to process these electrical signals have become a significant fundamental hardware in the development of the modern information industry. In any electrical circuitry, electrical signals have to be synchronized to a pulse for processing, transmitting, storing, and reading of those electrical signals. Different building blocks of an electrical structure usually have their timing synchronized to a pulse so the operation of different pulses such as the generation of pulses, the synchronization of pulses, the difference and adjustment of the pulses, and the multiplication and division of the frequency of pulses during synchronization are all the foremost research areas in the information technology industry.
Phase-locked loop and delay-locked loop are the most common type of building blocks used in circuits for operating pulse. Please refer to FIG. 1, it is a block diagram showing the functionality of a conventional phase-locked loop 10. the phase-locked loop 10 comprises a phase and frequency detector 12, a charge pump 14, a low pass filter 16, a voltage control oscillator 20, and two frequency dividers 18A, 18B. The detector 12 having two input terminals detects the frequency and phase difference of the inputted signals from the input terminals and sends out the results of the difference to the charge pump 14; the charge pump 14 is coupled to the low pass filter 16 for transforming the detection results of the detector 12 into corresponding voltage signals. The voltage control oscillator 20 receives the voltage signal output from the low pass filter 16 and generates a pair of pulses 24B whose frequency corresponds to the level of the voltage signal from the low pass filter 16. 1/Ka divider 18A divides the pulse 24A to become 26A so the frequency of the pulse 26A (counting the periods backwards) is 1/Ka of the frequency of the pulse 24A. The pulse 26A is sent back to the input terminal of the detector 12. Similarly the 1/Kb divider 18B can divide the pulse 24B to become the pulse 26B so the frequency of the pulse 26B is 1/Kb of that of the pulse 24B. The pulse 26B is sent back to the other input terminal of the detector 12.
The phase-locked loop 10 uses pulse 24A as a standard to generate and synchronize pulse 24A which stabilizes the frequency multiplication of pulse 24B. The operation of the phase-locked loop 10 is described in the following. The detector 12 detects the frequency and phase difference between the pulses 26A, 26B and transforms the difference into a voltage signal with the charge pump 14 and the low pass filter 16. The frequency of the pulse 24B is correspondingly adjusted by the voltage control oscillator 20. After the adjustment of the frequency of the pulse 24B the frequency of the pulse 26B is at the same time changed. The frequency and phase difference of the pulses 26B, 26A are again tested by the detector 12 and then sent through the charge pump 14 and low pass filter 16 to the voltage control oscillator 20 to control the frequency of pulse 24B. The above process for adjusting the frequency of the pulse 24B by the voltage control oscillator 20 according to the pulses 26A, 26B is repeated until the frequency and phase difference between the pulses 26A, 26B are zero therefore both frequency and time are synchronized. The phase-locked loop 10 completes the locking and the voltage control oscillator 20 can steadily output pulse 26B which is exactly in synchronization in frequency and time with the pulse 26A. As a result the pulses 26A, 26B are locked together. The frequency of pulse 24B (counting periods backwards) is the (Kb/Ka) fraction of the pulse 24A because the pulses 26A, 26B are divided by 1/Ka, 1/Kb respectively therefore Fb=(Kb/Ka)Fa, wherein Fa, Fb are the frequencies of the pulses 24A, 24B.
Apart from showing the conventional layout of the phase-locked loop 10, FIG. 1 also shows the conventional structure of the voltage control oscillator 20. The voltage control oscillator 20 can be made up of a plurality of differential buffers 22 (the differential buffer in the furthest left), wherein an input terminal (labeled as +) and an output terminal (labeled −) are separately electrically connected to the junction of between Na0 and Na5. The second differential buffer is electrically connected between Na5 and Na1 and so forth. The last differential buffer (the furthest right differential buffer in FIG. 1) is electrically connected to the junction between Na4 and Na9. The junctions Na9, Na10 are electrically connected together as well so the each differential buffer 22 is coupled to form a ring oscillator. The low pass filter 16 outputs a voltage signal to change the time delay of each differential buffer 22 which also changes the period of the pulse 24B. To further explain this phenomenon, please refer to FIG. 2 (and simultaneously refer to FIG. 1). FIG. 2 is a schematic diagram of the timing of the signal wave at different junctions of the voltage control oscillator 20. The horizontal axis represents time and the vertical axis represents the signal level. The waves C0, C1, C2, and the like till C9 represent the waves at the junction Na0, Na1, Na2, and the like to Na9 during the operation of the voltage control oscillator 20 in FIG. 1. The time period Td1 in FIG. 2 represents the delay time introduced by the differential buffer 22. For example, the wave C0 rises from a level low L to a level high H at time tp0 then the wave C5 at the junction Na5 falls from the level high H to the level low L at time tp1 after the furthest left differential buffer 22 introduces a time delay of Td1. Similarly, after the wave C5 shifts from the level high H to the level low L at tp1, the following differential buffer is activated so at tp2 (by adding a time delay Td1 from tp1) the wave C1 at the junction Na1 rises from the level low L to the level high H. By using the same process, each differential buffer 22 will activate the following differential buffer 22 to reverse the output signal after a time delay Td1 is applied. The furthest right differential buffer 22 in FIG. 1 shifts the wave C9 at the junction Na9 from the level high H to the level low L at tp3. The wave C0 (actually is also the wave C9) will again shifts level and this process repeats itself throughout the differential buffers. The voltage control oscillator 20 causes the waves C0 to C9 at the junctions Na0 to Na9 to swap and oscillate for outputting the pulse 24B (the waves C0, C9) at the junction Na9.
Please refer to FIG. 2, the waves C0 to C9 at the junctions Na0 to Na9 all have a period of T0 which is the time delay Td1 multiplied by the number of differential buffers 22 (there are nine differential buffers in FIG. 1, 2) and then further multiplied by 2. The low pass filter 16 outputs a voltage signal which can change the time delay Td1 introduced by each of the differential buffer 22 to control the frequency of the pulse 24B. From FIG. 2, the time delay introduced by the differential buffer 22 forms the phase difference between C1 and C9 (C0) causing the phase difference between the waves C1 and C9 to be evenly distributed within the 360 degrees that corresponds to the period T0.
Apart from the phase-locked loop, the delay-locked loop is also a commonly found building block in the circuits for operating pulse. Please refer to FIG. 3 which is schematic diagram of a conventional delay-locked loop 30 accompanied by two pulses circuits 28A, 28B. The delay-locked loop 20 comprises a detector 32, a charge pump 34, a low pass filter 36, and a variable control delay line (VCDL) 40. The detector 32 has two input terminals for detecting the phase difference of the two inputted signals. The charge pump 34 and the low pass filter 36 transforms the detection results from the detector 32 into voltage signals and transmits them to the delay-locked loop 40. The delay-locked loop 40 receives a pulse 46A and inserts a predefined time delay into the pulse 46A according to voltage signal from the low pass filter 36 and outputs a pulse 46B.
The delay-locked loop 30 synchronizes the pulse 46A, 46B without any phase difference. In modern electronic circuits (especially digital circuits), different circuit blocks usually require synchronized operation so a synchronized pulse with no phase difference (i.e. the rise and fall edge of signals have no time difference) is necessary for synchronized activation of different circuit blocks. In FIG. 3, the pulse circuits 28A, 28B are circuit blocks that are required to be activated simultaneously (for example, the pulse circuits 28A, 28B further comprise a plurality of logic gates, flip-flops, state machines, and the like). In order to activate and drive the different circuit blocks, the pulse needs to have an appropriate level of driving power. However a delay is experienced when using buffers to increase the level of the pulse and therefore a time difference (phase difference) exists in the original pulse. As a result the original pulse and the increased-power pulse cannot simultaneously trigger different circuit blocks. Under this circumstance, a delay-locked loop is required to generate two synchronized pulses with no phase difference for simultaneously using two different signals to drive two different circuit blocks. In FIG. 2, the delay-locked loop 30 generates another synchronized pulse 46B with no phase difference which uses pulses 46A, 46B to trigger the pulses circuits 28A, 28B needing synchronization. The operation of the delay-locked loop 30 is described in the following. The detector 32 detects the phase difference between the pulses 46A, 46B, and then charge pump 34 and the low pass filter 36 transform the phase difference into a voltage signal. After receiving the voltage signal, the delay-locked loop 40 will correspondingly adjust the phase difference of the pulse 46B. The detector 32 will again detect the phase difference between the pulse 46B and the pulse 46A and the delay-locked loop 40 will again adjust the pulse of the 46B according to the charge pump 34 and the low pass filter 36. The above process is repeated by adjusting the pulse 46B by the delay-locked loop 40 until there is no phase difference between the pulses 46A, 46B. As this instant, the pulses 46A, 46B are synchronized with no phase difference.
As illustrated in FIG. 3, the conventional delay-locked loop 40 comprises a plurality of buffers 42 (FIG. 3 is illustrated with nine buffers as an example) and each buffer is coupled to one another so a time delay can be applied to the input and output terminals according to the voltage signal outputted by the low pass filter 36. Taking the furthest left buffer 42 in FIG. 3 as an example, the input and output terminal are separately electrically connected between the junctions Nb0 and Nb1 to insert a time delay into the signal at the junctions Nb0, Nb1. Please refer back to FIG. 2 (simultaneously refer to FIG. 3), the waves C0, C1, and the like to C9 can be signals from the delay-locked loop 40 at the junctions Nb0, Nb1, and the like to Nb9. In FIG. 3, after the furthest left buffer 42 receives the pulse 46A of the wave C0 at the junction Nb0, a time delay Td2 is inserted to generate the wave C1 at the junction Nb1. Similarly, another buffer will insert another time delay Td2 to the signal at the junction Nb1 to generate the wave C2 at the junction Nb2. The process is repeated until the furthest left buffer 42 in FIG. 3 outputs the wave C9 at the junction Nb9 which is the pulse 46B. As illustrated in FIG. 2, when the pulses 46A, 46B are synchronized and locked, the phase difference between the waves C0 and C9 is actually one period T0 (or a period multiplied by an integer) of the wave C0. At this instant the rising and falling edge of the waves C0, C9 have no phase difference. The voltage control oscillator 20 in FIG. 1 unavoidably generates a predetermined phase difference in the waves C1 to C9 which is evenly distributed over the 360 degrees of the period T0 when the delay-locked loop 40 locks and synchronizes 46A, 46B at the junction Nb1 to Nb9.
The phase-locked loop and delay-locked loop shown in FIG. 1 and FIG. 3 are common building blocks for operating pulse but the conventional apparatus cannot sufficiently handle the wide application and contemporaneous requirement of the pulse requirement. Firstly in terms of the phase-locked loop as shown and described in FIG. 1, the phase-locked loop 10 generates a pulse 46B according to a pulse 24A and the relationship between them is defined by a multiplication factor: Fb=(Kb/Ka)Fa (which is the frequency of the pulses 24A, 24B). Theoretically speaking, adjusting the divide ratio 1/Ka or 1/Kb of the dividers 18A, 18B can generate the pulse 24B having different frequencies according to the pulse 24A. However in real application, the divide ratio affects the stability of the phase-locked loop so randomly interfering the divide ratio of the dividers 18A, 18B will cause the phase-locked loop 10 to become unstable. The divider 18B is especially affected because it is located in the feedback path of the phase-locked loop 10 which more easily affects the stability of the phase-locked loop 10. Different electronic circuits and different operational needs require different phase-locked loop having frequency multipliers (i.e. the above Kb/Ka). From the perspective of the IC designer, it is ideal that a design of a phase-locked loop being widely applicable to various electronic circuits by merely adjusting the divide ratio of the divider to create a phase-locked loop having different frequency multiplications. Apparently as mentioned, performing any random adjustment to the divide ratio of the dividers will cause instability of the phase-locked loop so the exact phase difference of two pulses cannot be obtained and the phase-locked loop fails. The conventional structure in FIG. 1 cannot be realistically made into a phase-locked loop having difference frequency multiplications because all other components such as the charge pump 14, the low pass filter 16, and the voltage control oscillator 20, have to be correspondingly changed besides changing the divide ratio of the divider to prevent instability from happening. In other words, the fundamental structure of the conventional phase-locked loop 10 lacks the flexibility and margin in design. In order to achieve a phase-locked loop with different frequency multiplication in different electronic circuits, other circuits in the phase-locked loop 10 along with the divide ratio and the divider have to be changed altogether. As a result, in order to adapt the conventional phase-locked loop, a lot of time and effort is required for redesigning, modeling, laying out, manufacturing, and the like which increase the time and cost in the manufacturing and design of electronic circuits.
Furthermore the delay-locked loop 30 in FIG. 3 does not have any frequency multiplication feature which can only maintain the synchronization of the pulses 46A, 46B without phase difference and cannot generate a pulse having difference frequency multiplication according to the pulse 46A. Therefore the pulse operation is limited.